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Proceedings Paper

Effects of ILD thickness and slope-etch depth on via performance and metal filling characteristics
Author(s): Gregory W. Grynkewich; John L. Freeman; Wayne K. Morrow; Ping Wang; Robert Woodburn
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Paper Abstract

The interaction of ILD (interlevel dielectric) thickness with slope etch depth on the performance of single and stacked vias has been characterized on a four-layer metal high performance bipolar device. Both wet and dry slope etches, which have significantly different cross sectional profiles, were investigated. As expected, the aspect ratio (AR) of the vertical wall of the via was critical in determining how well the via filled with hot Al/Cu: at AR > 0.8, some open vias were observed. However, it was also found that excessive dry slope etch could cause via performance to degrade. For a given ILD thickness, increasing the depth of the dry slope etch could cause via resistance to increase. In addition, for a constant RIE time (varied ILD thickness), deeper slope etches resulted in higher via resistance. These results are discussed in terms of an interaction between the dry slope etch and the amount of RIE overetch time.

Paper Details

Date Published: 15 September 1993
PDF: 10 pages
Proc. SPIE 2090, Multilevel Interconnection: Issues That Impact Competitiveness, (15 September 1993); doi: 10.1117/12.156532
Show Author Affiliations
Gregory W. Grynkewich, Motorola (United States)
John L. Freeman, Motorola (United States)
Wayne K. Morrow, Motorola (United States)
Ping Wang, Motorola (United States)
Robert Woodburn, Motorola (United States)


Published in SPIE Proceedings Vol. 2090:
Multilevel Interconnection: Issues That Impact Competitiveness
Hoang Huy Hoang; Ron Schutz; Joseph B. Bernstein; Barbara Vasquez, Editor(s)

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