As the VLSI/ULSI device density is increasing common failure mechanisms, such as internal latch-up phenomenon in sea-of-gate ASIC devices, are surfacing and becoming an important reliability issue. The traditional latch-up phenomenon sensitivity assessment techniques are no longer adequate; because the phenomenon is not limited to causes externally induced at the device peripherals but in process-induced defects as well. Therefore, an understanding of this effect is critical to both manufacturing and engineering communities. The purpose of this paper is to report a study of latch-ups in sea-of-gate (continuous arrays) ASIC devices. Two techniques, traditional and laser-induced testings, are presented.

Date Published: 15 September 1993
PDF: 4 pages
Proc. SPIE 2090, Multilevel Interconnection: Issues That Impact Competitiveness, (15 September 1993); doi: 10.1117/12.156527

Published in SPIE Proceedings Vol. 2090:
Multilevel Interconnection: Issues That Impact Competitiveness
Hoang Huy Hoang; Ron Schutz; Joseph B. Bernstein; Barbara Vasquez, Editor(s)