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Proceedings Paper

Wafer level reliability: competitiveness and implementation issues
Author(s): Jeff S. May; Hoang Huy Hoang
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Paper Abstract

How does wafer level reliability assessment and testing methodology integrate into the semiconductor manufacturer's overall reliability assurance and improvement strategy? What wafer level tests are appropriate and when should they be utilized? Wafer level reliability has made the evolutionary step from academia to manufacturing actuality. This paper provides a conceptual focus for where and when wafer level reliability is utilized in a state-of-the-art semiconductor manufacturing environment. Special emphasis is placed on the use of wafer level reliability testing for introducing and qualifying new semiconductor technology, as well as controlling production once the technology has been qualified.

Paper Details

Date Published: 15 September 1993
PDF: 7 pages
Proc. SPIE 2090, Multilevel Interconnection: Issues That Impact Competitiveness, (15 September 1993); doi: 10.1117/12.156521
Show Author Affiliations
Jeff S. May, SGS-Thomson Microelectronics (United States)
Hoang Huy Hoang, SGS-Thomson Microelectronics (United States)


Published in SPIE Proceedings Vol. 2090:
Multilevel Interconnection: Issues That Impact Competitiveness
Hoang Huy Hoang; Ron Schutz; Joseph B. Bernstein; Barbara Vasquez, Editor(s)

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