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Application of APCVD TEOS/ozone thin films in < 0.5-um IC fabrication: trench and intermetal dielectric isolation and gap fill
Author(s): Jeff P. West; H. Wallace Fry; Stephen Poon; B. A. Boeck; Chris C. Yu
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Paper Abstract

Basic film and process characteristics in conjunction with electrical test results are presented showing the effect of implementing a void free oxide for both intermetal and shallow trench isolation. An integrated intermetal dielectric (IMD) process is evaluated on fully functional 0.5 micrometers BiCMOS memory circuits. The integrated process uses two different films, an oxide for gap fill deposited at atmospheric pressure (APCVD) using a TEOS/O3 chemistry, and a second oxide deposited from TEOS using plasma enhanced CVD(PETEOS) for planarization, stress management, and moisture protection. The effect of a thin PETEOS barrier between TEOS/O3 and the underlying metal is explored, and some issues concerning the integration of chemical mechanical polishing into a void free backend process flow are investigated. The suitability of undoped APCVD TEOS/O3 thin films for isolation trench fill is also characterized and described. Process variable which determine the relevant properties for trench fill are evaluated. Well-behaved MOS transistors with excellent parasitic performance were achieved using trench isolation and are reported.

Paper Details

Date Published: 15 September 1993
PDF: 10 pages
Proc. SPIE 2090, Multilevel Interconnection: Issues That Impact Competitiveness, (15 September 1993); doi: 10.1117/12.156516
Show Author Affiliations
Jeff P. West, Motorola (United States)
H. Wallace Fry, Watkins-Johnson Co. (United States)
Stephen Poon, Motorola (United States)
B. A. Boeck, Motorola (United States)
Chris C. Yu, Motorola (United States)

Published in SPIE Proceedings Vol. 2090:
Multilevel Interconnection: Issues That Impact Competitiveness
Hoang Huy Hoang; Ron Schutz; Joseph B. Bernstein; Barbara Vasquez, Editor(s)

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