Share Email Print

Proceedings Paper

Methodology for generating behavioral specifications of analog hardware for artificial neural network implementations
Author(s): Arun Achyuthan; Mohamed I. Elmasry
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

The non-ideal behavior of analog integrated circuits make it necessary that Artificial Neural Network (ANN) systems be evaluated for the effect of error due to the non-idealities on its performance, before they are implemented in analog hardware. In this paper we describe a procedure for automatically evaluating a given ANN system, described in the form of a Data Flow Graph (DFG). The equations required for the quantitative evaluation are extracted from the DFG description using symbolic computation techniques. Optimization methods are applied for generating bounds on the maximum values of error that can be associated with each circuit block. The generated bounds are put back to behavioral models of individual circuits blocks in the design library, to help screening viable alternatives and to generate circuit level specifications. The methodology forms part of a design automation environment that helps to map ANN systems to hardware interconnection descriptions.

Paper Details

Date Published: 2 September 1993
PDF: 10 pages
Proc. SPIE 1965, Applications of Artificial Neural Networks IV, (2 September 1993); doi: 10.1117/12.152569
Show Author Affiliations
Arun Achyuthan, Univ. of Waterloo (Canada)
Mohamed I. Elmasry, Univ. of Waterloo (Canada)

Published in SPIE Proceedings Vol. 1965:
Applications of Artificial Neural Networks IV
Steven K. Rogers, Editor(s)

© SPIE. Terms of Use
Back to Top