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Proceedings Paper

Neural network models in wafer fabrication
Author(s): Chinmoy B. Bose; Herbert A. Lord
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Paper Abstract

Semiconductor wafer fabrication processing is becoming extremely complex as we strive for the continuous reduction of the minimum feature size of devices and for controlling the variability at each of the ever-increasing number of steps. Equipment/process models based on physical and chemical laws are difficult to build due to the process complexities. The non- linearity exhibited by many processes may restrict application of linear or quadratic statistical models to a very small operating range. The same remarks apply for feed-back control of a highly non-linear process. In this work we have generated predictor models using neural network and statistical response surface techniques for the Chemical Vapor Deposition (CVD) silicon epitaxy process. The prediction (generalization) performance of the neural network is appreciable better than both the linear and the quadratic response surface models. The comparative performance of the neural network model is expected to improve even further in representing more complex input-output relationships. We have also determined an inverse process model using neural network. An inverse process model is expected to be useful for determining the process control parameters when a specific output (scaler or vector) is required. It has also helped us identify the critical control parameters for the CVD process.

Paper Details

Date Published: 2 September 1993
PDF: 10 pages
Proc. SPIE 1965, Applications of Artificial Neural Networks IV, (2 September 1993); doi: 10.1117/12.152552
Show Author Affiliations
Chinmoy B. Bose, AT&T Bell Labs. (United States)
Herbert A. Lord, AT&T Bell Labs. (United States)


Published in SPIE Proceedings Vol. 1965:
Applications of Artificial Neural Networks IV
Steven K. Rogers, Editor(s)

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