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Proceedings Paper

Scalable VLSI parallel pipelined architecture for discrete wavelet transform
Author(s): Henry Y.H. Chuang; Ling Chen; Ching-Chung Li
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Paper Abstract

The discrete wavelet transform (DWT) provides a new method for signal/image analysis where high frequency components are studied with finer time resolution and low frequency components with coarser time resolution. It decomposes a signal or an image into localized contributions for multiscale analysis. This paper presents a parallel pipelined array processor for 1-dimensional (1-D) DWT. Unlike other VLSI DWT processors which processes signal data sequentially in a pipeline, this array processor can process all data in a signal segment in parallel and successive segments in the same pipeline which computes the multiple levels (octaves) of DWT. The speedup is linearly proportional to the width of the array (or the size of a segment), and thus the architecture is scalable.

Paper Details

Date Published: 6 August 1993
PDF: 8 pages
Proc. SPIE 2064, Machine Vision Applications, Architectures, and Systems Integration II, (6 August 1993); doi: 10.1117/12.150312
Show Author Affiliations
Henry Y.H. Chuang, Univ. of Pittsburgh (United States)
Ling Chen, Univ. of Pittsburgh (United States)
Ching-Chung Li, Univ. of Pittsburgh (United States)


Published in SPIE Proceedings Vol. 2064:
Machine Vision Applications, Architectures, and Systems Integration II
Bruce G. Batchelor; Susan Snell Solomon; Frederick M. Waltz, Editor(s)

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