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Proceedings Paper

Field-programmable gate array implementation of a systolic architecture for a morphology engine
Author(s): Abdelaziz Chihoub; M. LaValva; J. Avins; Jeff Turlip
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Paper Abstract

While morphology use is gaining in popularity, it can be a computationally intensive process. This is particularly true for applications requiring large structuring elements. In this paper we will describe the use of field programmable gate arrays (Xilinx 4000 FPGA family) to implement a systolic architecture for a morphology engine. The engine has a 14 bit data-path, a reconfigurable structuring element size and a 512 X 512 image size. We will describe the architecture, the FPGA implementation of the engine and the interface with the host (datacube).

Paper Details

Date Published: 6 August 1993
PDF: 12 pages
Proc. SPIE 2064, Machine Vision Applications, Architectures, and Systems Integration II, (6 August 1993); doi: 10.1117/12.150276
Show Author Affiliations
Abdelaziz Chihoub, Siemens Corporate Research, Inc. (United States)
M. LaValva, Siemens Corporate Research, Inc. (United States)
J. Avins, Siemens Corporate Research, Inc. (United States)
Jeff Turlip, Siemens Corporate Research, Inc. (United States)


Published in SPIE Proceedings Vol. 2064:
Machine Vision Applications, Architectures, and Systems Integration II
Bruce G. Batchelor; Susan Snell Solomon; Frederick M. Waltz, Editor(s)

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