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Proceedings Paper

Scalable architectures for image processing
Author(s): K. I. Diamantaras; Abdelaziz Chihoub; Andrzej Zawadzki
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Paper Abstract

Our study consists of three phases: mapping the algorithms on the three topologies, simulating the execution of these algorithms, and design of the array. Our mapping follows the standard methodology proposed for the design of systolic arrays, since our application domain is very specific and the selected algorithms very regular. After the mapping is done we simulate the algorithms using the SES/workbench simulation package which allows us to collect statistics on the execution time and efficiency of our mappings and evaluate the performance of the three topologies in our application domain using different array and problem sizes. For each algorithm and topology the range of scalability is determined as a function of image size. In the design phase we propose an SIMD array with 2-D torus interconnection topology as a cost- efficient solution to the scalable implementation of the selected algorithms. Considerations entering the design phase are performance as determined by simulations, cost of implementation, and ease of scaling the machine size.

Paper Details

Date Published: 6 August 1993
PDF: 12 pages
Proc. SPIE 2064, Machine Vision Applications, Architectures, and Systems Integration II, (6 August 1993); doi: 10.1117/12.150275
Show Author Affiliations
K. I. Diamantaras, Siemens Corporate Research, Inc. (United States)
Abdelaziz Chihoub, Siemens Corporate Research, Inc. (United States)
Andrzej Zawadzki, Siemens Corporate Research, Inc. (United States)


Published in SPIE Proceedings Vol. 2064:
Machine Vision Applications, Architectures, and Systems Integration II
Bruce G. Batchelor; Susan Snell Solomon; Frederick M. Waltz, Editor(s)

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