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Proceedings Paper

Matching of multiple-wafer steppers for 0.35-um lithography using advanced optimization schemes
Author(s): Martin A. van den Brink; Chris G. M. de Mol; Judon M. D. Stoeldraijer
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Paper Abstract

Lithographic equipment for processes with 0.35 micrometers design rules is becoming available. One of the critical questions is which imaging technology will be used to define the required small feature size. Another question, frequently underestimated, is how to achieve the required overlay requirement of 120 nm between randomly chosen machines. A general methodology to maintain the matched machine overlay has been reported earlier. However, since it is believed that a mix of lithographic tools will be used at 0.35 micrometers , namely DUV and i-line, the task of multiple machine matching is even more challenging: the overlay has to be maintained between two different types of steppers. The lens matching required--also between DUV and i- line lenses--is found to be 70 nm. In this paper we will report on the matched overlay performance of 14 machines, resulting in data from 52 matched random pairs of both DUV and i-line ASML steppers. The matching methodology is optimized to maintain optimum performance between random pairs of machines. This includes the use of reference wafers, matching simulation and stepper selection. Furthermore, we investigated different matching mathematics and their influence on matching performance. We show that the 120 nm overlay requirement can be achieved using multiple machines in a production environment. The paper concludes with a device overlay budget analysis.

Paper Details

Date Published: 4 August 1993
PDF: 20 pages
Proc. SPIE 1926, Integrated Circuit Metrology, Inspection, and Process Control VII, (4 August 1993); doi: 10.1117/12.148937
Show Author Affiliations
Martin A. van den Brink, ASM Lithography BV (Netherlands)
Chris G. M. de Mol, ASM Lithography BV (Netherlands)
Judon M. D. Stoeldraijer, ASM Lithography BV (Netherlands)

Published in SPIE Proceedings Vol. 1926:
Integrated Circuit Metrology, Inspection, and Process Control VII
Michael T. Postek, Editor(s)

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