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Proceedings Paper

Parallel processor for real-time structural control
Author(s): Bert L. Tise
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Paper Abstract

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-to-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection to host computer, parallelizing code generator, and look- up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating- point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An OpenWindows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.

Paper Details

Date Published: 22 July 1993
PDF: 9 pages
Proc. SPIE 1919, Smart Structures and Materials 1993: Mathematics in Smart Structures, (22 July 1993); doi: 10.1117/12.148404
Show Author Affiliations
Bert L. Tise, Sandia National Labs. (United States)


Published in SPIE Proceedings Vol. 1919:
Smart Structures and Materials 1993: Mathematics in Smart Structures
H. Thomas Banks, Editor(s)

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