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Proceedings Paper

Modular architecture for smart pixel switching networks
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Paper Abstract

Multistage interconnection networks based on the perfect shuffle topology are often suggested as candidates for large scale multiprocessor and broadband communication networks. The perfect shuffle interconnection requires global communication links that extend across the entire system and have a large number of wire crossovers. These constraints prohibit a scalable electronic implementation both within a VLSI chip and at the MCM or board levels. This paper presents the architecture of a scalable optoelectronic hardware module for building multistage interconnection networks. To achieve a scalable implementation, the design uses free-space optical interconnects for global communication links and electronic VLSI technology for local communication links and switching elements (e.g., smart pixel approach). Our approach is to engineer a network with the desired functionality, cost, and performance characteristics using generic hardware modules. In this paper, various applications are examined and their implementation using the proposed method is described.

Paper Details

Date Published: 1 July 1993
PDF: 12 pages
Proc. SPIE 1849, Optoelectronic Interconnects, (1 July 1993); doi: 10.1117/12.147086
Show Author Affiliations
Fouad E. Kiamilev, Univ. of North Carolina/Charlotte (United States)
Ashok V. Krishnamoorthy, Univ. of California/San Diego (United States)
Sadik C. Esener, Univ. of California/San Diego (United States)


Published in SPIE Proceedings Vol. 1849:
Optoelectronic Interconnects
Ray T. Chen, Editor(s)

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