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Proceedings Paper

GaAs heteroepitaxy with submicron Si CMOS: an experimental compatibility study
Author(s): Lawrence Anthony Hornak; Stuart K. Tewksbury; Homi E. Nariman
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Paper Abstract

Routine use of optical interconnections in MCM based computing systems ideally favors monolithic integration to achieve both high density and manufacturability. The central issue facing this monolithic evolutionary path is the compatibility of both III-V semiconductor growth and subsequent optoelectronic device and passive optical interconnection processing with existing and future generations of CMOS and advanced packaging technology. The influence of GaAs heteroepitaxy and device processing on submicron CMOS is the subject of an ongoing program seeking to experimentally determine compatibility conflicts and through understanding of their physical mechanisms identify directions for achieving GaAs heteroepitaxy compatibility with future CMOS generations. Following a brief review of GaAs heteroepitaxy compatibility concerns, preliminary results from the current experimental program exploring the influence of both thermally simulated and actual GaAs heteroepitaxy on commercial 0.9 micrometers (0.6 micrometers minimum channel length) CMOS are presented including parametric device modeling, interface state, and hot electron measurements of experimental test lot devices.

Paper Details

Date Published: 1 July 1993
PDF: 10 pages
Proc. SPIE 1849, Optoelectronic Interconnects, (1 July 1993); doi: 10.1117/12.147077
Show Author Affiliations
Lawrence Anthony Hornak, West Virginia Univ. (United States)
Stuart K. Tewksbury, West Virginia Univ. (United States)
Homi E. Nariman, West Virginia Univ. (United States)

Published in SPIE Proceedings Vol. 1849:
Optoelectronic Interconnects
Ray T. Chen, Editor(s)

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