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Proceedings Paper

Prototype coprocessor for image algebra operations
Author(s): Patrick C. Coffield; Matthew B. Scudiere
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Paper Abstract

The logical architecture for this effort was developed at Wright Laboratory. Oak Ridge National Laboratory has taken the design and reordered the data flow to allow a physical architecture to be prototypes using DSP chips, transputers, or VLSI. The design allows image algebra operations to be executed in a staged pipeline at nearly the same throughput as a memory to memory transfer. The control is by direct memory access from the host, in this case a SUN SPARC II. Reduce operations such as sum, maximum, and minimum are captured as by-products of the pipeline operation.

Paper Details

Date Published: 23 June 1993
PDF: 7 pages
Proc. SPIE 2030, Image Algebra and Morphological Image Processing IV, (23 June 1993); doi: 10.1117/12.146670
Show Author Affiliations
Patrick C. Coffield, Air Force Wright Lab. (United States)
Matthew B. Scudiere, Oak Ridge National Lab. (United States)

Published in SPIE Proceedings Vol. 2030:
Image Algebra and Morphological Image Processing IV
Edward R. Dougherty; Paul D. Gader; Jean C. Serra, Editor(s)

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