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Proceedings Paper

CCD operation using the high-speed imager test station
Author(s): Kevin L. Albright; George J. Yates; Nicholas S. P. King; Thomas E. McDonald; Bojan T. Turko
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Paper Abstract

The use of a high-speed (up to 100 MHz) programmable pattern generator and special clock driver/translator circuits for clocking solid-state multiple output imagers is discussed. A specific example of clocking a developmental 256 X 512 two-port CCD is illustrated. Reference to a prior report of clocking an eight-port CCD is included. Future use in clocking a CID imager is discussed.

Paper Details

Date Published: 1 January 1993
PDF: 8 pages
Proc. SPIE 1801, 20th International Congress on High Speed Photography and Photonics, (1 January 1993); doi: 10.1117/12.145796
Show Author Affiliations
Kevin L. Albright, Los Alamos National Lab. (United States)
George J. Yates, Los Alamos National Lab. (United States)
Nicholas S. P. King, Los Alamos National Lab. (United States)
Thomas E. McDonald, Los Alamos National Lab. (United States)
Bojan T. Turko, Lawrence Berkeley Lab. (United States)


Published in SPIE Proceedings Vol. 1801:
20th International Congress on High Speed Photography and Photonics
John Marks Dewey; Roberto G. Racca, Editor(s)

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