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Proceedings Paper

Control of stress-void formation in aluminum-copper filled vias
Author(s): John L. Freeman; Gordon Grivna; Clarence J. Tracy
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Paper Abstract

A four layer metal system, designed for high speed bipolar gate arrays, subjected to high temperature aging was found to contain mechanical stress induced voids at the metal to metal interfaces within micron and sub-micron vias. The interconnect metal used in the system, AlCu(1.5%) sputter deposited at high temperatures, literally fills the vias and is quite resistant to stress voiding in the lines. However, thermal aging at 200 degree(s)C with no current flow led to open circuit failures of the 0.8 micron stacked via structures where via two is place directly over via one, and within via one and via two chains as well. The time to failure was studied as a function of temperature, via dimension, and processing changes to both the surrounding dielectric and the metallization. Reliability studies of the original, unmodified via structure, as well as those with process changes as indicated above have identified some of the significant factors affecting stress controlled via reliability.

Paper Details

Date Published: 21 May 1993
PDF: 11 pages
Proc. SPIE 1805, Submicrometer Metallization: Challenges, Opportunities, and Limitations, (21 May 1993); doi: 10.1117/12.145477
Show Author Affiliations
John L. Freeman, Motorola, Inc. (United States)
Gordon Grivna, Motorola, Inc. (United States)
Clarence J. Tracy, Motorola, Inc. (United States)


Published in SPIE Proceedings Vol. 1805:
Submicrometer Metallization: Challenges, Opportunities, and Limitations
Thomas Kwok; Takamaro Kikkawa; Krishna Shenai, Editor(s)

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