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Proceedings Paper

Performance consideration for the scaling of submicron on-chip interconnections
Author(s): Yuh-J. Mii
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Paper Abstract

Effects of long wire RC delay to circuit and system performance are investigated for sub- micron on-chip interconnections corresponding to 0.75 to 0.25 micrometers CMOS technologies. A system performance model based on hypothetic microprocessors, projected from previous generations, is introduced for the performance analysis. From the analysis, it is found that non-scaled upper wiring levels (wide wires) for long global interconnections is the most effective approach to improve system performance with sub-micron-pitch interconnections. It can provide 70% performance improvement over the wide wire approach, which increase only wire width for long interconnections. The fat wire approach, however, requires some technology modifications, as well as one more wiring level than conventional approaches.

Paper Details

Date Published: 21 May 1993
PDF: 10 pages
Proc. SPIE 1805, Submicrometer Metallization: Challenges, Opportunities, and Limitations, (21 May 1993); doi: 10.1117/12.145476
Show Author Affiliations
Yuh-J. Mii, IBM Thomas J. Watson Research Ctr. (United States)


Published in SPIE Proceedings Vol. 1805:
Submicrometer Metallization: Challenges, Opportunities, and Limitations
Thomas Kwok; Takamaro Kikkawa; Krishna Shenai, Editor(s)

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