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Proceedings Paper

Electromigration and stress reliability in multilevel interconnect metallization
Author(s): Paul S. Ho; M. A. Moske; C. K. Hu
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Paper Abstract

As wiring interconnects evolve toward submicron and multilayered structures, electromigration and stress-induced failures become increasingly important for device yield and reliability. This paper discusses the present understanding of these reliability problems in multilevel interconnects formed with Al-based metallization. The multilevel structure and the submicron dimension alter the nature of the flux divergence, increasing the role of stud and interface in controlling damage formation. These effects are illustrated using the results of a recent study on electromigration failure in an advanced Al(Cu)/W two-level line/stud structure. To understand the mechanism for stress-induced void formation, the characteristics of thermal stress and stress relaxation in confined line structures are discussed. The confinement by the dielectric layer and the narrow width of the line are important factors in raising the stress level to cause void formation. Stress relaxation controls the kinetics of void growth and its mechanism is discussed.

Paper Details

Date Published: 21 May 1993
PDF: 14 pages
Proc. SPIE 1805, Submicrometer Metallization: Challenges, Opportunities, and Limitations, (21 May 1993); doi: 10.1117/12.145467
Show Author Affiliations
Paul S. Ho, Univ. of Texas/Austin (United States)
M. A. Moske, Univ. of Texas/Austin (United States)
C. K. Hu, IBM Thomas J. Watson Research Ctr. (United States)


Published in SPIE Proceedings Vol. 1805:
Submicrometer Metallization: Challenges, Opportunities, and Limitations
Thomas Kwok; Takamaro Kikkawa; Krishna Shenai, Editor(s)

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