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Proceedings Paper

Semi-integrated SOG/TEOS etchback process for multimetal submicron devices
Author(s): Nadia Iazzi; Luca Zanotti; Laura Bacci; Patrizia Vasquez
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Paper Abstract

A semi-integrated SOG/TEOS planarization process for intermetal dielectric (ILD) has been developed in the CVD cluster system Precision 5000 (Applied Materials). The process consists of SOG etch back performed in one chamber immediately followed by plasma TEOS deposition in another chamber of the system, to reduce particle contamination and moisture adsorption in the SOG film. The main goal of the work was to develop an etchback process with very low SOG/TEOS selectivity (i.e., 0.7:1) and good etch uniformity, suitable for VLSI planarization requirements. The results of the parametric process characterization performed with the CHF3/CF4/Ar chemistry and the very satisfactory defectivity levels obtained for interconnections and intermetal oxide, for contacts leakage and capacitor breakdown are reported. Special emphasis has been devoted to the study of the oxide interface after the etchback to correlate the probable surface modification to the `peeling' effect evidenced on the TEOS film. The advantages of using Ar sputter to solve the adhesion problem are then discussed.

Paper Details

Date Published: 16 April 1993
PDF: 12 pages
Proc. SPIE 1803, Advanced Techniques for Integrated Circuit Processing II, (16 April 1993); doi: 10.1117/12.142938
Show Author Affiliations
Nadia Iazzi, SGS-Thomson Microelectronics (Italy)
Luca Zanotti, SGS-Thomson Microelectronics (Italy)
Laura Bacci, SGS-Thomson Microelectronics (Italy)
Patrizia Vasquez, Applied Materials (Italy)

Published in SPIE Proceedings Vol. 1803:
Advanced Techniques for Integrated Circuit Processing II
James A. Bondur; Gary Castleman; Lloyd R. Harriott; Terry R. Turner, Editor(s)

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