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Proceedings Paper

Methodology for optimizing cost of ownership
Author(s): Rito A. Martinez; Veronica A. Czitrom; Neal G. Pierce; G. Scot Srodes
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Paper Abstract

A design of experiments methodology was used to evaluate seven different types of gate stack cluster tool configurations and their associated economic performance. SEMATECH's Cost of Ownership, Cost/Resource, Generic Dual, and Batch Cluster Tool Models plus ManSim and RS/1 were used. Response surface methodology (RSM) was utilized to predict and optimize the tool's configuration and economic performance parameters against three independent factory strategies. These strategies were: minimize cost per chip, minimize process cycle time, and increase capital utilization and flexibility. As expected, the single wafer tool configurations produced the lowest process step cycle times. Results also indicate that for a single wafer processing tool (at a cost of $1.2 M) to be economically viable (in terms of COO) as an alterative to the conventional approach, process times (per wafer, per chamber) of less than five minutes must be achieved. The batch cluster tool configuration with one pre-clean, gate oxide and poly chamber each was the best method to increase capital utilization and flexibility. This methodology can be applied to any process tool evaluation and can prove useful in designing and improving the tools's performance in order to meet factory goals.

Paper Details

Date Published: 16 April 1993
PDF: 25 pages
Proc. SPIE 1803, Advanced Techniques for Integrated Circuit Processing II, (16 April 1993); doi: 10.1117/12.142932
Show Author Affiliations
Rito A. Martinez, SEMATECH (United States)
Veronica A. Czitrom, SEMATECH (United States)
Neal G. Pierce, SEMATECH (United States)
G. Scot Srodes, SEMATECH (United States)

Published in SPIE Proceedings Vol. 1803:
Advanced Techniques for Integrated Circuit Processing II
James A. Bondur; Gary Castleman; Lloyd R. Harriott; Terry R. Turner, Editor(s)

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