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Proceedings Paper

Sloped etching of highly phosphorous doped polysilicon developed with response surface methodology
Author(s): Joerg Jasper
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Paper Abstract

Plasma etching of highly phosphorous doped polysilicon gate structures can yield undercutting of the poly lines creating a negative slope of the vertical edge of the polysilicon or a notching at the bottom of the lines. In order to achieve good step coverage of subsequent deposited oxides and to facilitate the removal of stringers during etching of a poly II layer in EEPROM structures, such a profile cannot be acceptable. This paper describes the development of a chlorine-based reactive ion etching (RIE) process that exhibits slightly positively sloped (85 degree(s) angle) profiles of the first polysilicon layer. Response surface methodology was used to identify most important process parameters and to characterize the final process. The results obtained at the different stages are presented in detail.

Paper Details

Date Published: 16 April 1993
PDF: 11 pages
Proc. SPIE 1803, Advanced Techniques for Integrated Circuit Processing II, (16 April 1993); doi: 10.1117/12.142914
Show Author Affiliations
Joerg Jasper, EM Microelectronic-Marin SA (Switzerland)

Published in SPIE Proceedings Vol. 1803:
Advanced Techniques for Integrated Circuit Processing II
James A. Bondur; Gary Castleman; Lloyd R. Harriott; Terry R. Turner, Editor(s)

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