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Proceedings Paper

Gate oxide damage and evaluation techniques
Author(s): Koichi Hashimoto; Daisuke Matsunaga; Masao Kanazawa
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Paper Abstract

The quantities of the gate damage in an ECR plasma are evaluated as charge-up gate currents with the technique which employs Al gate MOS diodes and their sensitive flat band voltage shifts with current stress. A general model for charge-up damage is proposed. A charge-up I- V characteristic in the ECR plasma is estimated applying this technique, showing good agreement with that derived from the model. It is also deduced that the same I-V of the test device as the real device is essentially required for the correct evaluation. In a barrel reactor damage, antennas do not show the simple current collecting effect which has been expected.

Paper Details

Date Published: 16 April 1993
PDF: 8 pages
Proc. SPIE 1803, Advanced Techniques for Integrated Circuit Processing II, (16 April 1993); doi: 10.1117/12.142913
Show Author Affiliations
Koichi Hashimoto, Fujitsu Ltd. (Japan)
Daisuke Matsunaga, Fujitsu Ltd. (Japan)
Masao Kanazawa, Fujitsu Ltd. (Japan)

Published in SPIE Proceedings Vol. 1803:
Advanced Techniques for Integrated Circuit Processing II
James A. Bondur; Gary Castleman; Lloyd R. Harriott; Terry R. Turner, Editor(s)

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