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Proceedings Paper

Microtrenching during polysilicon plasma etch
Author(s): Steve W. Swan; Daniel A. Corliss
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Paper Abstract

Micro-trenching occurs during plasma polysilicon etch for features with sub 0.5 micrometers spaces and thin gate dielectric. The trenches, which form near the base of etched features as a series of holes through the gate dielectric and into the underlying silicon, are the result of ion scattering off the resist/polysilicon sidewall. By studying structures with varying feature spacing and resist thicknesses we were able to determine that the depth and location of the trenches are related to the aspect ratio (height:width) of the structure, the sidewall profile of the resist/polysilicon line, and the process conditions during over-etch. Ion scattering which causes the micro-trenching is enhanced under conditions of increasing aspect ratio and decreasing sidewall angle of the etched feature.

Paper Details

Date Published: 16 April 1993
PDF: 11 pages
Proc. SPIE 1803, Advanced Techniques for Integrated Circuit Processing II, (16 April 1993); doi: 10.1117/12.142906
Show Author Affiliations
Steve W. Swan, Digital Equipment Corp. (United States)
Daniel A. Corliss, Digital Equipment Corp. (United States)

Published in SPIE Proceedings Vol. 1803:
Advanced Techniques for Integrated Circuit Processing II
James A. Bondur; Gary Castleman; Lloyd R. Harriott; Terry R. Turner, Editor(s)

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