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Proceedings Paper

1.0625-Gbit/s fiber channel transmitter/receiver chipset implemented in ECL with on-chip phase-locked loop
Author(s): Thomas G. Palkert; Frederick Taverdians; Sharon Weintraub; Bruce H. Coy; Ali Wehbi; Marc D. Friedmann
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Paper Abstract

A mixed signal Application-Specific Standard Product (ASSP) which integrates custom phase-locked loop (PLL) based clock recovery and clock synthesis functions with configurable logic cells provides a two-chip solution for 266 to 1062 Mbit/s Fiber Channel applications. The chipset performs parallel-to-serial and serial-to-parallel conversion, 8B/10B encoding/decoding functions, framing, and primitive signal/sequence generation and identification. The on-chip clock synthesis PLL generates the high-speed serial clock from a low-speed reference. The on-chip clock recovery PLL is capable of synchronizing directly to incoming digital signals, while simultaneously retiming and regenerating the data stream. The chips are designed using an advanced one-micron bipolar process with `Turbo' cells resulting in substantially reduced static power and output skews. Models for the PLL functions have been developed for use in logic simulation platforms. These models allow full chip-level and system-level simulation capabilities.

Paper Details

Date Published: 9 February 1993
PDF: 12 pages
Proc. SPIE 1784, High-Speed Fiber Networks and Channels II, (9 February 1993); doi: 10.1117/12.141091
Show Author Affiliations
Thomas G. Palkert, Applied Micro Circuits Corp. (United States)
Frederick Taverdians, Applied Micro Circuits Corp. (United States)
Sharon Weintraub, Applied Micro Circuits Corp. (United States)
Bruce H. Coy, Applied Micro Circuits Corp. (United States)
Ali Wehbi, Applied Micro Circuits Corp. (United States)
Marc D. Friedmann, Applied Micro Circuits Corp. (United States)

Published in SPIE Proceedings Vol. 1784:
High-Speed Fiber Networks and Channels II
Kadiresan Annamalai, Editor(s)

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