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Proceedings Paper

Analog CMOS contrastive Hebbian networks
Author(s): Christian Schneider; Howard Card
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Paper Abstract

CMOS VLSI circuits implementing an analog neural network with on-chip contrastive Hebbian learning and capacitive synaptic weight storage have been designed and fabricated. Weights are refreshed by periodic repetition of the training data. To evaluate circuit performance in a medium-sized system, these circuits were used to build a 132 synapse neural network. An adaptive neural system, such as the one described in this paper, can compensate for imperfections in the components from which it is constructed, and thus it is possible to build this type of system using simple, silicon area-efficient analog circuits. Because these analog VLSI circuits are far more compact than their digital counterparts, analog VLSI neural network implementations are potentially more efficient than digital ones.

Paper Details

Date Published: 16 September 1992
PDF: 10 pages
Proc. SPIE 1709, Applications of Artificial Neural Networks III, (16 September 1992); doi: 10.1117/12.140057
Show Author Affiliations
Christian Schneider, Univ. of Manitoba (Canada)
Howard Card, Univ. of Manitoba (Canada)


Published in SPIE Proceedings Vol. 1709:
Applications of Artificial Neural Networks III
Steven K. Rogers, Editor(s)

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