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Proceedings Paper

Analog storage of adjustable synaptic weights
Author(s): Damien Macq; Jean-Didier Legat; P. G.A. Jespers
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Paper Abstract

One of the most important specific problems faced in the analog implementation of neural networks is the storage of synaptic weights. They must have a long storage lifetime, be compact in size, and compatible with a multiplier. They also must be adjustable to provide an on-chip learning capability. The purpose of the circuit presented in this paper was to test the implementation of dynamically refreshed analog memories using conventional CMOS technology with special care in achieving high resolution with small silicon area, and small read-write access time. The circuit prototype presented in this paper implements adjustable analog synaptic weights, compatible with an analog multiplier. The synaptic weights are dynamically refreshed with an on-chip system based on A/D and D/A conversion. The circuit has been fully tested, and a resolution of 7 bits per memory cell was measured. These are arranged in an array of 14 X 15 cells. Dimensions of the circuit, including refreshment system, are 1.7 mm X 1.7 mm in a conservative 2.4 micrometers CMOS process. Translated to a more efficient process (<EQ 1 (mu) CMOS process), this corresponds to a density of +/- 500 memory cells per square millimeter.

Paper Details

Date Published: 16 September 1992
PDF: 7 pages
Proc. SPIE 1709, Applications of Artificial Neural Networks III, (16 September 1992); doi: 10.1117/12.140054
Show Author Affiliations
Damien Macq, Univ. Catholique de Louvain (Belgium)
Jean-Didier Legat, Univ. Catholique de Louvain (Belgium)
P. G.A. Jespers, Univ. Catholique de Louvain (Belgium)


Published in SPIE Proceedings Vol. 1709:
Applications of Artificial Neural Networks III
Steven K. Rogers, Editor(s)

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