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Proceedings Paper

Hardware design of a fast neural network digital multiplier
Author(s): Jayakuma Rudrupathy; Chia-Lun John Hu
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Paper Abstract

As reported previously, one can very efficiently convert an analog voltage to a clean M-valued digital number by using an M-zero neural network. Therefore, using these neural networks in conjunction with some analog arithmetic processors allows us to do the digital multiplication in a much more efficient way than the conventional binary multiplication. That is, we may have the advantages of the speed of the analog system and the accuracy of the M-valued digital system combined together in the new system. In this paper, we report the hardware design and the experimental result of the theoretical work that we previously published along this line.

Paper Details

Date Published: 16 September 1992
PDF: 4 pages
Proc. SPIE 1709, Applications of Artificial Neural Networks III, (16 September 1992); doi: 10.1117/12.140045
Show Author Affiliations
Jayakuma Rudrupathy, Southern Illinois Univ./Carbondale (United States)
Chia-Lun John Hu, Southern Illinois Univ./Carbondale (United States)

Published in SPIE Proceedings Vol. 1709:
Applications of Artificial Neural Networks III
Steven K. Rogers, Editor(s)

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