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Proceedings Paper

Maximization of nMOSFET hot-carrier injection stability through optimization of device and process design
Author(s): Harrison B. Haver; Shu-Wu Chiu; Thomas V. Meixner; James W. Miller
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Paper Abstract

The effects of several key wafer processing conditions on submicron n-channel MOS transistor hot-carrier injection stability have been studied. Specifically, the interactions of gate oxide interface integrity, lightly doped drain spacer length and ion implant parameters, polycrystalline silicon gate oxidation sequence, and source-drain ion implant and anneal conditions have been examined. After wafer fabrication, packaged test transistors were subjected to accelerated hot-carrier stress conditions. Hot-carrier injection damage was assessed by measuring and comparing critical transistor DC parameters before and after stress. The relative impact of hot-carrier generation and trapping efficiency on the degradation of linear regime drain current was analyzed and compared for each set of process conditions. Additionally, circuit parameters were examined to assess the impact of process and device modifications on performance. Finally, an optimum set of processing conditions have been identified which insure maximum device stability without compromising device or circuit performance.

Paper Details

Date Published: 14 January 1993
PDF: 14 pages
Proc. SPIE 1802, Microelectronics Manufacturing and Reliability, (14 January 1993); doi: 10.1117/12.139351
Show Author Affiliations
Harrison B. Haver, Motorola, Inc. (United States)
Shu-Wu Chiu, Motorola, Inc. (United States)
Thomas V. Meixner, Motorola, Inc. (United States)
James W. Miller, Motorola, Inc. (United States)

Published in SPIE Proceedings Vol. 1802:
Microelectronics Manufacturing and Reliability
Barbara Vasquez; Anant G. Sabnis; Kenneth P. MacWilliams; Jason C.S. Woo, Editor(s)

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