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Proceedings Paper

Wafer level reliability
Author(s): Theodore A. Dellin; William M. Miller; Donald G. Pierce; Eric S. Snyder
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Paper Abstract

This paper presents a perspective on the use of Wafer Level Reliability (WLR) in developing a competitive quality/reliability program. WLR is defined as accelerated stressing of test structures at the wafer level. The pros and cons of WLR are considered in five application areas: process control; qualification; benchmarking; reliability monitoring/prediction; and modeling. WLR examples are discussed in the areas of oxide breakdown, hot carrier degradation, and electromigration. The need to develop physical, statistical, and geometrical models to extrapolate from WLR results to actual products is discussed.

Paper Details

Date Published: 14 January 1993
PDF: 11 pages
Proc. SPIE 1802, Microelectronics Manufacturing and Reliability, (14 January 1993); doi: 10.1117/12.139345
Show Author Affiliations
Theodore A. Dellin, Sandia National Labs. (United States)
William M. Miller, Sandia National Labs. (United States)
Donald G. Pierce, Sandia National Labs. (United States)
Eric S. Snyder, Sandia National Labs. (United States)


Published in SPIE Proceedings Vol. 1802:
Microelectronics Manufacturing and Reliability
Barbara Vasquez; Anant G. Sabnis; Kenneth P. MacWilliams; Jason C.S. Woo, Editor(s)

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