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Proceedings Paper

Parallel processor simulator for multiple optic channel architectures
Author(s): Tom S. Wailes; David G. Meyer
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Paper Abstract

A parallel processing architecture based on multiple channel optical communication is described and compared with existing interconnection strategies for parallel computers. The proposed multiple channel architecture (MCA) uses MQW-DBR lasers to provide a large number of independent, selectable channels (or virtual buses) for data transport. Arbitrary interconnection patterns as well as machine partitions can be emulated via appropriate channel assignments. Hierarchies of parallel architectures and simultaneous execution of parallel tasks are also possible. Described are a basic overview of the proposed architecture, various channel allocation strategies that can be utilized by the MCA, and a summary of advantages of the MCA compared with traditional interconnection techniques. Also describes is a comprehensive multiple processor simulator that has been developed to execute parallel algorithms using the MCA as a data transport mechanism between processors and memory units. Simulation results -- including average channel load, effective channel utilization, and average network latency for different algorithms and different transmission speeds -- are also presented.

Paper Details

Date Published: 17 December 1992
PDF: 12 pages
Proc. SPIE 1787, Multigigabit Fiber Communications, (17 December 1992); doi: 10.1117/12.139314
Show Author Affiliations
Tom S. Wailes, Air Force Institute of Technology (United States)
David G. Meyer, Purdue Univ. (United States)

Published in SPIE Proceedings Vol. 1787:
Multigigabit Fiber Communications
Leonid G. Kazovsky; Karen Liu, Editor(s)

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