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Proceedings Paper

ECL gate array with integrated PLL-based clock recovery and synthesis for high-speed data and telecom applications
Author(s): David S. Rosky; Bruce H. Coy; Marc D. Friedmann
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Paper Abstract

A 2500 gate mixed signal gate array has been developed that integrates custom PLL-based clock recovery and clock synthesis functions with 2500 gates of configurable logic cells to provide a single chip solution for 200 - 1244 MHz fiber based digital interface applications. By customizing the digital logic cells, any of the popular telecom and datacom standards may be implemented.

Paper Details

Date Published: 1 March 1992
PDF: 10 pages
Proc. SPIE 1577, High-Speed Fiber Networks and Channels, (1 March 1992); doi: 10.1117/12.134921
Show Author Affiliations
David S. Rosky, Applied Micro Circuits Corp. (United States)
Bruce H. Coy, Applied Micro Circuits Corp. (United States)
Marc D. Friedmann, Applied Micro Circuits Corp. (United States)

Published in SPIE Proceedings Vol. 1577:
High-Speed Fiber Networks and Channels

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