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Proceedings Paper

Designing a VMEbus FDDI adapter card
Author(s): Raman Venkataraman
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Paper Abstract

This paper presents a system architecture for a VMEbus FDDI adapter card containing a node core, FDDI block, frame buffer memory and system interface unit. Most of the functions of the PHY and MAC layers of FDDI are implemented with National's FDDI chip set and the SMT implementation is simplified with a low cost microcontroller. The factors that influence the system bus bandwidth utilization and FDDI bandwidth utilization are the data path and frame buffer memory architecture. The VRAM based frame buffer memory has two sections - - LLC frame memory and SMT frame memory. Each section with an independent serial access memory (SAM) port provides an independent access after the initial data transfer cycle on the main port and hence, the throughput is maximized on each port of the memory. The SAM port simplifies the system bus master DMA design and the VMEbus interface can be designed with low-cost off-the-shelf interface chips.

Paper Details

Date Published: 1 March 1992
PDF: 11 pages
Proc. SPIE 1577, High-Speed Fiber Networks and Channels, (1 March 1992); doi: 10.1117/12.134910
Show Author Affiliations
Raman Venkataraman, National Semiconductor Corp. (United States)


Published in SPIE Proceedings Vol. 1577:
High-Speed Fiber Networks and Channels
Kadiresan Annamalai, Editor(s)

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