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Proceedings Paper

High-performance architecture for linear-camera vision systems
Author(s): John W. V. Miller; Mark Wilson
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Paper Abstract

While linear cameras offer substantial advantages over RS-170 cameras for many vision applications, the lack of suitable high-performance image-processing hardware has significantly limited their potential benefits. The very large images and high data rates associated with linear cameras impose significant processing problems that limit the capabilities of current linear-camera hardware designs. A highly desirable goal is to design new hardware architectures that will significantly improve processing capabilities to exploit the advantages of linear cameras without the need for frame buffers with their inherent restrictions on image size and format. This paper describes an approach that offers significant improvements for linear-camera based vision systems without requiring frame buffers. The proposed design advocates the use of lookup tables compatible with low-cost VLSI technology to perform extensive additional low-level processing. Hardware to perform data compression and extraction of key information from image data is also covered. The overall objectives of this architecture include providing low-cost hardware, flexibility, and ease of programming.

Paper Details

Date Published: 1 November 1992
PDF: 9 pages
Proc. SPIE 1823, Machine Vision Applications, Architectures, and Systems Integration, (1 November 1992); doi: 10.1117/12.132070
Show Author Affiliations
John W. V. Miller, Univ. of Michigan/Dearborn (United States)
Mark Wilson, Univ. of Michigan/Dearborn (United States)


Published in SPIE Proceedings Vol. 1823:
Machine Vision Applications, Architectures, and Systems Integration
Bruce G. Batchelor; Susan Snell Solomon; Frederick M. Waltz, Editor(s)

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