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Proceedings Paper

High-speed binary-image processor for reduction conversion and image rotation
Author(s): Hiroyuki Matsumoto; Ikuro Oyaizu
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Paper Abstract

A high-speed binary-image processor has been developed to perform reduction conversion while suppressing image degradation. The processor adopts two newly developed reduction- conversion methods: thin-line preservation reduction and multilevel display reduction, and also incorporates a 90-degree rotation function indispensable to image processing. For A4-size image data having a resolution of 200 dpi, the processor performs 1/3 reduction in 95 msec and rotation by 90 degrees in 66 msec.

Paper Details

Date Published: 1 November 1992
PDF: 12 pages
Proc. SPIE 1818, Visual Communications and Image Processing '92, (1 November 1992); doi: 10.1117/12.131375
Show Author Affiliations
Hiroyuki Matsumoto, NTT Human Interface Labs. (Japan)
Ikuro Oyaizu, NTT Human Interface Labs. (Japan)

Published in SPIE Proceedings Vol. 1818:
Visual Communications and Image Processing '92
Petros Maragos, Editor(s)

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