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Proceedings Paper

High-voltage MOS transistors compatible with CMOS VLSI technology
Author(s): Wlodzimierz Podmiotko
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Paper Abstract

In this paper high-voltage MOS transistors structures fabricated using a standard CMOS technology and a special design technique are presented. The design, characterization, and modeling of n-MOS, with the breakdown voltage of 50 V, and p-MOS, with the breakdown voltage of 130 V, fabricated using a standard 3 micrometers CMOS process are discussed. In addition, the possibility of high-voltage buffer circuit realization which is composed of n-MOS and p-MOS transistors, operating with the supply system USS equals 0, UDD equals 5 V, UE equals - 40 V, self-isolated from low-voltage components is demonstrated.

Paper Details

Date Published: 1 August 1992
PDF: 12 pages
Proc. SPIE 1783, International Conference of Microelectronics: Microelectronics '92, (1 August 1992); doi: 10.1117/12.131028
Show Author Affiliations
Wlodzimierz Podmiotko, Institute of Electron Technology (Poland)

Published in SPIE Proceedings Vol. 1783:
International Conference of Microelectronics: Microelectronics '92
Andrzej Sowinski; Jan Grzybowski; Witold T. Kucharski; Ryszard S. Romaniuk, Editor(s)

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