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Proceedings Paper

CUPLAND: behavioral level description compiler for designing of PLD-based circuits
Author(s): Stanislaw Deniziak; Krzysztof Sapiecha
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Paper Abstract

P-CAD's CUPL is one of the most popular tools for translating a functional description of the circuit into its corresponding PLD-based structure. However, CUPL's input format describes a circuit at the very low level. Moreover, it requires an early selection of target PLD devices that is particularly inconvenient when more complex circuitry is considered. Therefore, designing of large circuits with the help of CUPL is tiring and time consuming. In the paper, another concept is investigated. Behavioral description of the circuit is formulated using procedural CHDL called UPLAND. Then, this description is automatically translated into its corresponding CUPL input format where target PLD devices are optional. The paper introduces UPLAND and outlines the principles of CUPLAND compiler work. An example is given which illustrates CUPLAND efficiency.

Paper Details

Date Published: 1 August 1992
PDF: 8 pages
Proc. SPIE 1783, International Conference of Microelectronics: Microelectronics '92, (1 August 1992); doi: 10.1117/12.131021
Show Author Affiliations
Stanislaw Deniziak, Kielce Univ. of Technology and ResComp Kielce (Poland)
Krzysztof Sapiecha, Kielce Univ. of Technology and ResComp Kielce (Poland)

Published in SPIE Proceedings Vol. 1783:
International Conference of Microelectronics: Microelectronics '92
Andrzej Sowinski; Jan Grzybowski; Witold T. Kucharski; Ryszard S. Romaniuk, Editor(s)

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