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Proceedings Paper

Some checking algorithms of digital circuits testability
Author(s): Roman Kulesza; Andrzej Krzyztof Wach
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Paper Abstract

The theoretical basis of the research for the most advantageous way for isolation of the circuit clusters are given. The formal description of the circuit information net model, being the basis on the inference engine about the testability of the circuit are presented. The work has the goal of improvement of the computer-aided design of the digital circuits with the redundancy and/or built-in self-test.

Paper Details

Date Published: 1 August 1992
PDF: 8 pages
Proc. SPIE 1783, International Conference of Microelectronics: Microelectronics '92, (1 August 1992); doi: 10.1117/12.131017
Show Author Affiliations
Roman Kulesza, Military Technical Academy and Industrial Institute of Electronics (Poland)
Andrzej Krzyztof Wach, Industrial Institute of Electronics (Poland)

Published in SPIE Proceedings Vol. 1783:
International Conference of Microelectronics: Microelectronics '92
Andrzej Sowinski; Jan Grzybowski; Witold T. Kucharski; Ryszard S. Romaniuk, Editor(s)

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