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Proceedings Paper

Architecture and some properties of digital circuits with boundary scan
Author(s): Jerzy Kern
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Paper Abstract

The paper presents basic properties of digital circuits, with a boundary scan testing (BST) subsystem in the circuit architecture. The paper describes the operation and states for test access port controller (TAPC) built in the subsystem. A self-test procedure is presented, based on pseudo-random test generation and signature analysis, done by linear feedback shift registers (LFSR), configured with boundary scan register cells. Characteristics of the pseudo- random signal generator were obtained by simulation method.

Paper Details

Date Published: 1 August 1992
PDF: 12 pages
Proc. SPIE 1783, International Conference of Microelectronics: Microelectronics '92, (1 August 1992); doi: 10.1117/12.131016
Show Author Affiliations
Jerzy Kern, Industrial Institute of Electronics (Poland)

Published in SPIE Proceedings Vol. 1783:
International Conference of Microelectronics: Microelectronics '92
Andrzej Sowinski; Jan Grzybowski; Witold T. Kucharski; Ryszard S. Romaniuk, Editor(s)

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