Share Email Print
cover

Proceedings Paper

Device modeling for high-speed three-dimensional CMOS/SOI integrated circuits
Author(s): Konstantin O. Petrosjanc; Maria V. Sicheva
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

The physical effects in SOI MOSFETs such as the floating substrate regime in `thick' film, accumulation of excess holes in `thick' and `thin' film for the negative voltage at the back gate, the influence of the fixed surface charges at the front and back interface Si-SiO2 are investigated using two-dimensional numerical simulation. The dependence of the current- voltage characteristics of SOI MOSFET on the physical and technological parameters are analyzed. Some specific effects such as kink-effect, histeresis of drain characteristics, drain current overshoot, and their dependences on the switching speed are investigated. It is shown that thin film SOI devices with excluding floating substrate effects must be used for high speed VLSI. The switching characteristics of the different construction of the SOI/CMOS structures are simulated and compared. It is shown that thin film 3-D SOI/CMOS make a good choice for high speed VLSI.

Paper Details

Date Published: 1 August 1992
PDF: 7 pages
Proc. SPIE 1783, International Conference of Microelectronics: Microelectronics '92, (1 August 1992); doi: 10.1117/12.130999
Show Author Affiliations
Konstantin O. Petrosjanc, Moscow Institute of Electronic Engineering (Russia)
Maria V. Sicheva, Moscow Institute of Electronic Engineering (Russia)


Published in SPIE Proceedings Vol. 1783:
International Conference of Microelectronics: Microelectronics '92

© SPIE. Terms of Use
Back to Top