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Proceedings Paper

PLD-based synthesis of digital circuits
Author(s): Krzysztof Jasinski; Jerzy Kalinowski; Tadeusz Luba
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Paper Abstract

This paper addresses development of application specific integrated circuits in field programmable technologies using programmable logic devices (PLDs). Problems in designing on PLD devices are discussed, with emphasis on device-specific constraints. As a basic shortcoming of the existing automated design tools, lack of high level design procedures optimizing the actual circuit with respect to the target PLD device architectural capabilities is indicated. To support more effective utilization of PLD device mapping, special systems that exploit argument reduction and generic logic decomposition are proposed. Problems that have been encountered in designing a PCM frame synchronization circuit are discussed, to illustrate the whole spectrum of decisions to be made by the designer.

Paper Details

Date Published: 1 August 1992
PDF: 9 pages
Proc. SPIE 1783, International Conference of Microelectronics: Microelectronics '92, (1 August 1992); doi: 10.1117/12.130988
Show Author Affiliations
Krzysztof Jasinski, Warsaw Univ. of Technology (Poland)
Jerzy Kalinowski, Warsaw Univ. of Technology (Poland)
Tadeusz Luba, Warsaw Univ. of Technology (Poland)


Published in SPIE Proceedings Vol. 1783:
International Conference of Microelectronics: Microelectronics '92

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