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Optical Engineering

Architectures For Focal Plane Image Processing
Author(s): Eric R. Fossum
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Paper Abstract

Architectures for focal plane image processing are discussed. On-chip image preprocessing for solid-state imagers using analog CCD circuits is described for low, medium, and high density detector arrays. A spatially parallel architecture for low density, high throughput applications is described. For sparse illumination or event detection, a content-addressable architecture is proposed. A new pipelined vector pixel processor architecture for medium density infrared staring focal plane arrays is described. Neighborhood reconstruction during serial readout of high density TV-quality imagers for a pixel processor is considered using delay and analog frame memory techniques. The potential of on-chip read/write analog frame memory for image transformation and frame-to-frame processing is discussed.

Paper Details

Date Published: 1 August 1989
PDF: 7 pages
Opt. Eng. 28(8) doi: 10.1117/12.7977048
Published in: Optical Engineering Volume 28, Issue 8
Show Author Affiliations
Eric R. Fossum, Columbia University (United States)

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