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Optical Engineering

Optical Clock Distribution To Silicon Chips
Author(s): Bradley D. Clymer; Joseph W. Goodman
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Paper Abstract

Timing constraints for state-of-the-art very large scale integrated circuits (VLSI) in silicon are rapidly approaching communication limits available with layered two-dimensional metal and polysilicon wiring approaches. For such communication-limited systems, reliable clock distribution is a key concern. The range of finite differences in signal delays over clock wires of various lengths for large chips creates a timing skew that is significant when compared to the switching time of transistors in the circuit. The high bandwidth and three-dimensionality of imaging optical systems suggest that optical clock distribution systems have the potential to overcome the timing barriers presented by planar wiring. Clock signals can be holographically mapped to detector sites within small functional cells on a chip surface. Within each functional cell, the clock is distributed with negligible delays via surface wires, reducing skew effects to the variation in reaction times of the photodetectors on the chip. This paper includes the presentation of an optical clock distribution system assuming holographic mapping of beams from an off-chip optical source. Computer simulations of the electronic response of optical clock detection circuits in standard 4 µm CMOS technology have been performed.

Paper Details

Date Published: 1 October 1986
PDF: 6 pages
Opt. Eng. 25(10) doi: 10.1117/12.7973964
Published in: Optical Engineering Volume 25, Issue 10
Show Author Affiliations
Bradley D. Clymer, Stanford University (United States)
Joseph W. Goodman, Stanford University (United States)


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