Share Email Print

Optical Engineering

Automatic Flatness Tester For Very Large Scale Integrated Circuit Wafers
Author(s): Toyohiko Yatagai; Shigeru Inaba; Hideki Nakano; Masane Suzuki
Format Member Price Non-Member Price
PDF $20.00 $25.00

Paper Abstract

A high speed automatic flatness analysis system for very large scale integrated circuit wafers has been developed. By using the Fizeau interferometer, a contour map of a silicon wafer is generated, which is then analyzed with a digital image processing system. A special hardware system that performs basic image processing operations, including fringe-peak detection, fringe thinning, fringe-order labeling, local averaging, and so on, was developed. Warpage and undulation of the wafer, which are represented by special indices, are estimated. The surface is not contacted at all during measurement.

Paper Details

Date Published: 1 August 1984
PDF: 5 pages
Opt. Eng. 23(4) 234401 doi: 10.1117/12.7973308
Published in: Optical Engineering Volume 23, Issue 4
Show Author Affiliations
Toyohiko Yatagai, University of Tsukuba (Japan)
Shigeru Inaba, SG Instrument Ltd. (Japan)
Hideki Nakano, SG Instrument Ltd. (Japan)
Masane Suzuki, Fuji Photo-Optical Co. Ltd. (Japan)

© SPIE. Terms of Use
Back to Top