Share Email Print

Optical Engineering

Metal Oxide Semiconductor Technology Scaling Issues And Their Relation To Submicron Lithography
Author(s): Al F. Tasch, Jr.
Format Member Price Non-Member Price
PDF $20.00 $25.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

This paper examines the impact of submicron metal oxide semiconductor (MOS) integrated circuit technology on submicron lithography, and contrasts the lithography picture today with that for submicron features. A considerably larger number of factors must be dealt with rigorously because they either do not scale with decreasing dimensions or they do not lend themselves easily to more rigid control so that it has become disproportionately difficult to reduce their effect. In addition to the lithography issues, other serious device technology limitations arise at submicron dimensions. These have to do with device isolation, gate insulation, parasitic resistance and capacitance, interconnectivity, particle-induced upset, and hot electron effects. These issues must also be successfully resolved if submicron dimensions are to be successfully exploited in submicron integrated circuits.

Paper Details

Date Published: 1 April 1983
PDF: 5 pages
Opt. Eng. 22(2) 222176 doi: 10.1117/12.7973077
Published in: Optical Engineering Volume 22, Issue 2
Show Author Affiliations
Al F. Tasch, Jr., Motorola, Inc. (United States)

© SPIE. Terms of Use
Back to Top