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Optical Engineering

Submicron Lithography
Author(s): Phillip D. Blais
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Paper Abstract

Narrower linewidths have been axiomatically desirable in semiconductor device geometries for over two decades, while rapid improvements in optical lithography were largely responsible for the tremendous growth rate in integrated circuits. Projecting the course of future development in lithography is perilous, however, because we are approaching serious limitations in both device design and optical lithography. This special issue of Optical Engineering is aimed at clarifying some technical factors that will affect the course of development, and it properly begins with an introduction to the subject by A. F. Tasch. Tasch carefully considers a growing awareness that registration at each edge on the etched substrate is the most important issue in nanometer lithography, and that major obstacles also exist in scaling down the size of metal oxide semiconductor (MOS) devices. A slow pace in finding solutions to device design limitations may retard the need for reducing linewidth and, in turn, profoundly affect the future course of nanometer lithography.

Paper Details

Date Published: 1 April 1983
PDF: 1 pages
Opt. Eng. 22(2) 222175 doi: 10.1117/12.7973076
Published in: Optical Engineering Volume 22, Issue 2
Show Author Affiliations
Phillip D. Blais, Westinghouse Electrical Corporation (United States)

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