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Journal of Electronic Imaging

High-speed hardware architecture for high-definition videotex system
Author(s): Mitsuru Maruyama; Hiroaki Sakamoto; Yutaka Ishibashi; Kazutoshi Nishimura
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Paper Abstract

A high-speed hardware architecture for an experimental high-definition videotex system for a broadband integrated services digital network is introduced. The key technologies required are high-speed protocol processing, high-speed data transfer, and high-speed picture readout from disks. High-speed protocol processing using a newly developed virtual memory copy, content rearrangement memory, two-bus architecture, and simultaneous editing and analyzing allows a requested 6-MB picture to be displayed within 3 s.

Paper Details

Date Published: 1 October 1992
PDF: 9 pages
J. Electron. Imaging. 1(4) doi: 10.1117/12.60922
Published in: Journal of Electronic Imaging Volume 1, Issue 4
Show Author Affiliations
Mitsuru Maruyama, NTT Human Interface Labs. (Japan)
Hiroaki Sakamoto, NTT Human Interface Labs. (Japan)
Yutaka Ishibashi, NTT Human Interface Labs. (Japan)
Kazutoshi Nishimura, NTT Human Interface Labs. (Japan)


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