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Journal of Electronic Imaging

High-quality image processing architecture for facsimiles
Author(s): Keisuke Nakashima; Shin'ichi Shinoda; Yasuyuki Kojima; Yasuro Hori; Toshiaki Nakamura; Noboru Suemori
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Paper Abstract

A total and coherent image processing architecture for G3/G4/ISDN facsimiles is proposed that features high-quality multi-level processing by means of correlative area scanning and a software-oriented processing architecture. This image processing LSI controller includes a resolution converter and error diffusion halftone processing circuits in 4000 gates. A semi-superfine scanning mode is evaluated, which will be adopted as a new CCITT G3 optional mode.

Paper Details

Date Published: 1 January 1992
PDF: 7 pages
J. Electron. Imag. 1(1) doi: 10.1117/12.55179
Published in: Journal of Electronic Imaging Volume 1, Issue 1
Show Author Affiliations
Keisuke Nakashima, Hitachi Ltd. (Japan)
Shin'ichi Shinoda, Hitachi Ltd. (Japan)
Yasuyuki Kojima, Hitachi Ltd. (Japan)
Yasuro Hori, Hitachi Ltd. (Japan)
Toshiaki Nakamura, Hitachi Ltd. (Japan)
Noboru Suemori, Hitachi Ltd. (Japan)

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