Share Email Print

Optical Engineering

Novel alignment technique for 0.1-μm lithography using the wafer rear surface and canceling tilt effect
Author(s): Souichi Katagiri; Shigeo Moriyama; Tsuneo Terasawa
Format Member Price Non-Member Price
PDF $20.00 $25.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

A new wafer rear surface alignment (RSA) technique using a rear surface and canceling tilt effect (RECT) for wafer steppers is proposed. RECT alignment can provide the alignment accuracies of less than 0.03 μm (3σ) that are required for 0.1-μm lithography. The accuracy is almost the same as the resolution limit in the alignment sensor; therefore, position detection errors, which are caused by multi-interference in resist films and the asymmetric profile of marks deformed during manufacturing processes, must be decreased until they can be neglected. The concept of wafer RSA has provided a breakthrough to obtain higher overlay accuracy by fabricating alignment marks on the wafer rear surface. RSA, however, has the disadvantage of a position detection error ε caused by a thickness between the wafer surface and the rear surface, which strongly depends on the wafer tilt. To overcome this problem, RECT consists of two-beam-illumination optics to cancel the error ε. The diffracted beams that are reflected from two separate points on the grating mark include information on both mark positions and light-path difference due to wafer tilt. Thus, the wafer-tilt-induced error can be automatically canceled by processing this information. In an experiment using a six-axis fine positioning stage, it was proven that alignment accuracy can be minimized to as small as 0.015 μm (3σ) for a wafer-tilt angle range of ±50 μrad.

Paper Details

Date Published: 1 October 1993
PDF: 6 pages
Opt. Eng. 32(10) doi: 10.1117/12.145957
Published in: Optical Engineering Volume 32, Issue 10
Show Author Affiliations
Souichi Katagiri, Hitachi, Ltd. (Japan)
Shigeo Moriyama, Hitachi, Ltd. (Japan)
Tsuneo Terasawa, Hitachi, Ltd. (Japan)

© SPIE. Terms of Use
Back to Top