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Optical Engineering

Hardware architecture for full analytical Fraunhofer computer-generated holograms
Author(s): Zhi-Yong Pang; Zong-Xi Xu; Yi Xiong; Biao Chen; Hui-Min Dai; Shao-Ji Jiang; Jian-Wen Dong
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Paper Abstract

Hardware architecture of parallel computation is proposed for generating Fraunhofer computer-generated holograms (CGHs). A pipeline-based integrated circuit architecture is realized by employing the modified Fraunhofer analytical formulism, which is large scale and enables all components to be concurrently operated. The architecture of the CGH contains five modules to calculate initial parameters of amplitude, amplitude compensation, phases, and phase compensation, respectively. The precalculator of amplitude is fully adopted considering the “reusable design” concept. Each complex operation type (such as square arithmetic) is reused only once by means of a multichannel selector. The implemented hardware calculates an 800×600  pixels hologram in parallel using 39,319 logic elements, 21,074 registers, and 12,651 memory bits in an Altera field-programmable gate array environment with stable operation at 50 MHz. Experimental results demonstrate that the quality of the images reconstructed from the hardware-generated hologram can be comparable to that of a software implementation. Moreover, the calculation speed is approximately 100 times faster than that of a personal computer with an Intel i5-3230M 2.6 GHz CPU for a triangular object.

Paper Details

Date Published: 3 September 2015
PDF: 8 pages
Opt. Eng. 54(9) 095101 doi: 10.1117/1.OE.54.9.095101
Published in: Optical Engineering Volume 54, Issue 9
Show Author Affiliations
Zhi-Yong Pang, Sun Yat-Sen Univ. (China)
Zong-Xi Xu, Sun Yat-Sen Univ. (China)
Yi Xiong, Sun Yat-Sen Univ. (China)
Biao Chen, Sun Yat-Sen Univ. (China)
Hui-Min Dai, Sun Yat-Sen Univ. (China)
Shao-Ji Jiang, Sun Yat-Sen Univ. (China)
Jian-Wen Dong, Sun Yat-Sen Univ. (China)

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