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Journal of Micro/Nanolithography, MEMS, and MOEMS

Lithographic imaging-driven pattern edge placement errors at the 10-nm node
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Paper Abstract

As new microelectronic designs are being developed, the demands on image overlay and pattern dimension control are compounded by requirements that pattern edge placement errors (EPEs) be at a single-nanometer levels. Scanner performance plays a key role in determining location of the pattern edges at different device layers, not only through overlay but also through imaging performance. The imaging contributes to edge displacement through the variations of the image dimensions and by shifting the images from their target locations. We discuss various aspects of advanced image control relevant to a 10-nm node integrated circuit design. We review a range of issues of pattern edge placement directly linked to pattern imaging. We analyze the impact of different pattern design and scanner-related edge displacement drivers. We present two examples of imaging strategies to pattern logic device metal layer cuts. We analyze EPEs of the cut images resulting from optimized layout design and scanner setup, and we draw conclusions on edge placement control versus imaging performance requirements.

Paper Details

Date Published: 30 March 2016
PDF: 11 pages
J. Micro/Nanolith. 15(2) 021402 doi: 10.1117/1.JMM.15.2.021402
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 15, Issue 2
Show Author Affiliations
Jacek K. Tyminski, Nikon Research Corp. of America (United States)
Julia A. Sakamoto, Nikon Research Corp. of America (United States)
Shane R. Palmer, Nikon Research Corp. of America (United States)
Stephen P. Renwick, Nikon Research Corp. of America (United States)


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